The subject invention is directed generally to boundary scan test cells, and is directed more particularly to input and output boundary scan test cells having programmable mask capability.
Boundary scan testing is commonly utilized to test the interconnections between digital devices that comprise a system, where the interconnected devices can include integrated circuits, application specific integrated circuits (ASICs), hybrids, and circuit boards, for example. For boundary scan test capability, a device includes scan circuits that are capable of isolating device I/O pins from the interior logic of the device and directly accessing such I/O pins, which allows special interconnection test patterns to be applied and observed without interference from the interior logic functions.
Boundary scan test capability is commonly implemented with boundary scan cells respectively associated with those I/O pins for which boundary scan testing capability is being provided, with each boundary scan cell containing a scan flip-flop. The scan flip-flops are arranged into a register chain that is capable of operation in serial and parallel modes, so that test patterns can be loaded serially, applied in parallel, and test results can be read out serially.
For testing, special interconnection test patterns are serially loaded into scan flip-flops for output pins,. After a test pattern is loaded, the output scan cells containing the test pattern are switched to drive their associated output pins in accordance with the test pattern. Subsequently, the signals observed on input pins are stored in associated input scan flip-flops. The stored inputs are then serially read out to evaluate the test. A further test pattern can be serially loaded into output scan flip-flops while stored inputs are being serially read out.
Boundary scan test patterns are basically designed to achieve the following:
1. To drive each device output under test to the high state and to the low state at different times. Proper reception at the appropriate inputs verifies continuity. PA1 2. To drive each device output under test to the state opposite that of all other outputs, for both the low state and the high state. A short circuit between two or more outputs will be indicated by contention between the shorted drivers. PA1 1. In applications where outputs from a plurality of devices share a common bus, contention is prevented by allowing only one device to be active on the bus at any given time. The outputs of the devices which are not active on the bus are controllably masked, for example by being held in the high impedance state (commonly designated by the letter Z). PA1 2. During interconnect testing of an application that includes memories, chip enable or write enable signals provided by a boundary scanned device to the memories must be held at a level (1 or 0 depending upon implementation) to prevent unintended writing of data into memory. PA1 3. While a particular device is being internally tested, interconnections between its interior and its outputs must be held in fixed state (typically, but not always, the Z state) so as to avoid conflicts with other devices, which may be simultaneously under test, or which may be continuing to function while the device under test performs a concurrent self test. PA1 4. When a device is a multi-chip module (MCM), and interconnections between its I/O pins and those of other MCMs are being tested, it is desirable to mask off the I/O internal to the MCM, which allows external I/O errors to be differentiated from internal I/O errors when signatures are used for response evaluation. PA1 5. During interconnect testing, certain inputs may be in a "don't care," but indeterminate, state. When signatures are used for response evaluation, it is important to hold these in a known state. Masking allows the indeterminate state to be disregarded, and a known state substituted. PA1 6. It is often desirable to perform logic tests (as opposed to interconnect tests) which involve 2 or more, but not all, connected devices. Input masking provides a means of excluding interference from devices not participating in such tests.
The paper "INTERCONNECT TESTING WITH BOUNDARY SCAN," Wagner, IEEE Proc. 1987 International Test Conference, pages 52-57, generally describes the application and implementation of boundary scan testing, and test patterns that allow for efficient boundary scan testing.
When tests are preformed on digital systems, it is often necessary or preferable to hold particular device outputs at predetermined logic states and/or to disregard the signal at a device input. This may be done for various reasons including the following:
The required masking may be a part of a stored test pattern set. However, it is often desirable to use hard-wired algorithms to generate tests, and to use signature evaluators for the response, which results in a more efficient, faster test. When hardwired algorithmic tests are used with known boundary scan cells, the required masking is typically achieved by placing those boundary cells to be masked into separate serial scan chains (or groups). Since there may be many such chains on a VLSI integrated circuit (IC), the design becomes complex. The numerous chains must all be accessed and controlled by typically a single serial test bus which accesses the IC. Further, the I/O pins associated with a group are preferentially placed in a physically contiguous manner in order to make the layout and routing of the IC as efficient as possible, but this is often impossible to achieve. Further, known practice requires that the I/O of a lower assembly or device which are connected to the I/O of a higher assembly (i.e., which contains the lower assembly or device) be placed in special scan groups. This prevents the use of that assembly or device in any other higher assembly that requires different connections to its I/O.